drivers/gpu/drm/i915/intel_gvt_mmio_table.c

709

MMIO_F(_MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000);

drivers/gpu/drm/i915/intel_mchbar_regs.h

125

#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)

drivers/gpu/drm/i915/intel_mchbar_regs.h

128

#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)

drivers/gpu/drm/i915/intel_mchbar_regs.h

132

#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)

drivers/gpu/drm/i915/intel_mchbar_regs.h

140

#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)

drivers/gpu/drm/i915/intel_mchbar_regs.h

141

#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)

drivers/gpu/drm/i915/intel_mchbar_regs.h

142

#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)

drivers/gpu/drm/i915/intel_mchbar_regs.h

161

#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)

drivers/gpu/drm/i915/intel_mchbar_regs.h

162

#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)

drivers/gpu/drm/i915/intel_mchbar_regs.h

198

#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)

drivers/gpu/drm/i915/intel_mchbar_regs.h

205

#define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930)

drivers/gpu/drm/i915/intel_mchbar_regs.h

213

#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)

drivers/gpu/drm/i915/intel_mchbar_regs.h

217

#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)

drivers/gpu/drm/i915/intel_mchbar_regs.h

219

#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)

drivers/gpu/drm/i915/intel_mchbar_regs.h

221

#define PCU_PACKAGE_TEMPERATURE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978)

drivers/gpu/drm/i915/intel_mchbar_regs.h

224

#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)

drivers/gpu/drm/i915/intel_mchbar_regs.h

225

#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)

drivers/gpu/drm/i915/intel_mchbar_regs.h

230

#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)

drivers/gpu/drm/i915/intel_mchbar_regs.h

232

#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)

drivers/gpu/drm/i915/intel_mchbar_regs.h

240

#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)

drivers/gpu/drm/i915/intel_mchbar_regs.h

253

#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)

drivers/gpu/drm/i915/intel_mchbar_regs.h

254

#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)

drivers/gpu/drm/i915/intel_mchbar_regs.h

261

#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)

drivers/gpu/drm/i915/intel_mchbar_regs.h

266

#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)

drivers/gpu/drm/i915/intel_mchbar_regs.h

99

#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

21

#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

30

#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

35

#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

37

#define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

40

#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)

drivers/gpu/drm/xe/xe_guc_pc.c

42

#define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)

drivers/gpu/drm/xe/xe_guc_pc.c

47

#define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)