AR_SM_BASE
#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
#define AR_PHY_PAPRD_TRAINER_CNTL1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x580 : 0x490))
#define AR_PHY_PAPRD_TRAINER_CNTL2(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x584 : 0x494))
#define AR_PHY_PAPRD_TRAINER_CNTL3(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x588 : 0x498))
#define AR_PHY_PAPRD_TRAINER_CNTL4(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x58c : 0x49c))
#define AR_PHY_PAPRD_TRAINER_STAT1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x590 : 0x4a0))
#define AR_PHY_PAPRD_TRAINER_STAT2(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x594 : 0x4a4))
#define AR_PHY_PAPRD_TRAINER_STAT3(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x598 : 0x4a8))
#define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
#define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)
#define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
#define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
#define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
#define AR_PHY_MODE (AR_SM_BASE + 0x8)
#define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
#define AR_PHY_SPUR_MASK_A(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x18 : 0x20))
#define AR_PHY_SPUR_MASK_B(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x1c : 0x24))
#define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
#define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
#define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
#define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
#define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
#define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
#define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
#define AR_PHY_RIFS (AR_SM_BASE + 0x44)
#define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
#define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
#define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
#define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
#define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
#define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
#define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
#define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
#define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
#define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
#define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
#define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
#define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
#define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
#define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
#define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
#define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
#define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
#define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
#define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
#define AR_PHY_TEST(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x15c : 0x160))
#define AR_PHY_TEST_CTL_STATUS(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x160 : 0x164))
#define AR_PHY_TSTDAC(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x164 : 0x168))
#define AR_PHY_CHAN_STATUS(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x168 : 0x16c))
#define AR_PHY_CHAN_INFO_MEMORY(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x16c : 0x170))
#define AR_PHY_CHNINFO_NOISEPWR(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x170 : 0x174))
#define AR_PHY_CHNINFO_GAINDIFF(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x174 : 0x178))
#define AR_PHY_CHNINFO_FINETIM(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x178 : 0x17c))
#define AR_PHY_CHAN_INFO_GAIN_0(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x17c : 0x180))
#define AR_PHY_SCRAMBLER_SEED(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x184 : 0x190))
#define AR_PHY_CCK_TX_CTRL(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x188 : 0x194))
#define AR_PHY_HEAVYCLIP_CTL(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x198 : 0x1a4))
#define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
#define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
#define AR_PHY_HEAVYCLIP_1 (AR_SM_BASE + 0x19c)
#define AR_PHY_HEAVYCLIP_2 (AR_SM_BASE + 0x1a0)
#define AR_PHY_HEAVYCLIP_3 (AR_SM_BASE + 0x1a4)
#define AR_PHY_HEAVYCLIP_4 (AR_SM_BASE + 0x1a8)
#define AR_PHY_HEAVYCLIP_5 (AR_SM_BASE + 0x1ac)
#define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
#define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
#define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
#define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
#define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
#define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
#define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
#define AR_PHY_TX_IQCAL_CONTROL_0(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \
#define AR_PHY_TX_IQCAL_CONTROL_1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \
#define AR_PHY_TX_IQCAL_START(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \
#define AR_PHY_TX_IQCAL_STATUS_B0(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \
#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_ah, _i) (AR_SM_BASE + \
#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
#define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)
#define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)
#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
#define AR_PHY_BB_THERM_ADC_3 (AR_SM_BASE + 0x250)
#define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
AR_SM1_BASE : AR_SM_BASE))
AR_SM1_BASE : AR_SM_BASE))
#define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
#define AR_PHY_AIC_SRAM_ADDR_B0 (AR_SM_BASE + 0x5f0)
#define AR_PHY_AIC_SRAM_DATA_B0 (AR_SM_BASE + 0x5f4)