drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

652

static_assert(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

574

static_assert(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

573

static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

699

if (i > MAX_NUM_DPM_LVL - 1)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

700

i = MAX_NUM_DPM_LVL - 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

503

static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1130

if (i > MAX_NUM_DPM_LVL - 1)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1131

i = MAX_NUM_DPM_LVL - 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

560

ASSERT(num_levels <= MAX_NUM_DPM_LVL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

561

if (num_levels > MAX_NUM_DPM_LVL)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

562

num_levels = MAX_NUM_DPM_LVL;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

224

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

313

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

220

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

319

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2649

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2796

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3143

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3238

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

365

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

724

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

814

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

186

struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2287

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

118

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

141

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

164

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

187

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

46

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

69

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

92

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

109

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

125

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

137

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

56

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

61

for (j = 0; j < MAX_NUM_DPM_LVL; j++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

78

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

92

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {