drivers/gpu/drm/amd/display/dc/dc_dp_types.h

226

uint8_t MAX_LANE_COUNT:5;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1394

link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1934

link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;

drivers/gpu/drm/bridge/ite-it6505.c

1365

it6505->lane_count = MAX_LANE_COUNT;

drivers/gpu/drm/bridge/ite-it6505.c

1878

u8 lane_level_config[MAX_LANE_COUNT] = { 0 };

drivers/gpu/drm/bridge/ite-it6505.c

1951

u8 lane_level_config[MAX_LANE_COUNT] = { 0 };

drivers/gpu/drm/bridge/ite-it6505.c

3355

*max_lane_count = MAX_LANE_COUNT;

drivers/gpu/drm/bridge/ite-it6505.c

3359

*max_lane_count = MAX_LANE_COUNT;

drivers/gpu/drm/bridge/ite-it6505.c

492

u8 voltage_swing[MAX_LANE_COUNT];

drivers/gpu/drm/bridge/ite-it6505.c

493

u8 pre_emphasis[MAX_LANE_COUNT];