MC2
saa7146_read(dev, MC2);
saa7146_write(dev, MC2, 0xf8000000);
if (saa7146_read(dev, MC2) & 2)
saa7146_read(dev, MC2);
if (saa7146_read(dev, MC2) & 2)
saa7146_write(dev, MC2, (MASK_02|MASK_18));
u32 mc2 = saa7146_read(dev, MC2);
saa7146_write(dev,MC2, MASK_31);
saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
saa7146_write(dev, MC2, (MASK_05 | MASK_21));
saa7146_write(dev, MC2, (MASK_05 | MASK_21));
saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1)));
WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));
saa7146_write(dev, MC2, (MASK_05 | MASK_21));
saa7146_write(dev, MC2, MASK_27 );
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
saa7146_write(dev, MC2, (MASK_00 | MASK_16));
mc2 = (saa7146_read(dev, MC2) & 0x1);
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
saa7146_write(dev, MC2, (MASK_04|MASK_20));
saa7146_write(dev, MC2, MASK_04|MASK_20);
saa7146_write(dev, MC2, (MASK_08|MASK_24));
saa7146_write(dev, MC2, MASK_31|MASK_15);
saa7146_write(dev, MC2, MASK_04|MASK_20);
saa7146_write(dev, MC2, MASK_27 );
saa7146_write(dev, MC2, MASK_22 | MASK_06);
saa7146_write(dev, MC2, MASK_22 | MASK_06);
saa7146_write(dev, MC2, MASK_22 | MASK_06);
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, MASK_09 | MASK_25 | MASK_10 | MASK_26);
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_08 | MASK_24));
saa7146_write(dev, MC2, (MASK_04 | MASK_20));
saa7146_write(saa, MC2, (2 << 16) | 2);
saa7146_write(saa, MC2, (2 << 16) | 2);
saa7146_write(dev, MC2, (MASK_09 | MASK_25));
saa7146_write(dev, MC2, (MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25));
saa7146_write(dev, MC2, (MASK_10 | MASK_26));
saa7146_write(dev, MC2,
saa7146_write(dev, MC2, (MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, MASK_08 | MASK_24);
saa7146_write(dev, MC2, MASK_04 | MASK_20);
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, 0x077c077c);
saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, 0x077c077c);
saa7146_write(av7110->dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (2 << 16) | 2);
saa7146_write(dev, MC2, (2 << 16) | 2);
saa7146_write(av7110->dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */