MC1
saa7146_write(dev, MC1, 0x30ff0000);
saa7146_write(dev, MC1, 0x00ff0000);
saa7146_write(dev,MC1, MASK_20);
saa7146_write(dev, MC1, (MASK_12 | MASK_28));
saa7146_write(dev, MC1, (MASK_10 | MASK_26));
WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
saa7146_write(dev, MC1, MASK_21);
saa7146_write(dev, MC1, (MASK_12 | MASK_28));
saa7146_write(dev, MC1, (MASK_08 | MASK_24));
saa7146_write(dev, MC1, (MASK_13 | MASK_29));
saa7146_write(dev, MC1, MASK_20);
saa7146_write(dev, MC1, MASK_29);
WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
saa7146_write(dev, MC1, (MASK_13 | MASK_29));
saa7146_write(dev, MC1, MASK_29);
saa7146_write(dev, MC1, MASK_20);
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
saa7146_write(dev, MC1, MASK_28);
saa7146_write(dev, MC1, dmas);
saa7146_write(dev, MC1, (MASK_08 | MASK_24 | MASK_10 | MASK_26));
saa7146_write(dev, MC1, (MASK_08 | MASK_24 | MASK_10 | MASK_26));
saa7146_write(saa, MC1, MASK_27 | MASK_11);
saa7146_write(saa, MC1, MASK_27);
saa7146_write(saa, MC1, MASK_27);
saa7146_write(saa, MC1, MASK_27 | MASK_11);
saa7146_write(saa, MC1, MASK_27);
saa7146_write(saa, MC1, MASK_27);
saa7146_write(dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */
saa7146_write(budget->dev, MC1, MASK_20); // DMA3 off
saa7146_write(dev, MC1, MASK_20); // DMA3 off
saa7146_write(budget->dev, MC1, MASK_20); /* DMA3 off */
saa7146_write(budget->dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */
saa7146_write(dev, MC1, MASK_31);
saa7146_write(dev, MC1, MASK_29);
saa7146_write(dev, MC1, (MASK_13 | MASK_29));
saa7146_write(dev, MC1, (MASK_29));
saa7146_write(dev, MC1, (MASK_13 | MASK_29));
saa7146_write(saa, MC1, MASK_29);
saa7146_write(saa, MC1, MASK_20); /* DMA3 off */
saa7146_write(av7110->dev, MC1, 0x08800880);
WRITEREG((EAP << 16) | EAP, MC1);
WRITEREG((EI2C << 16) | EI2C, MC1);
WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
WRITEREG((TR_E_A2_OUT << 16), MC1);
WRITEREG((TR_E_A1_OUT << 16), MC1);
WRITEREG((TR_E_A1_IN << 16) | TR_E_A1_IN, MC1);
WRITEREG((TR_E_A1_IN << 16), MC1);
WRITEREG((MRST_N << 16), MC1);
WRITEREG((MRST_N << 16), MC1);