drivers/gpu/drm/amd/display/dc/core/dc.c

3470

ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

610

if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

634

ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

677

if (dwb_pipe_inst >= MAX_DWB_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

682

if (stream->num_wb_info > MAX_DWB_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

713

if (dwb_pipe_inst >= MAX_DWB_PIPES) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

718

if (stream->num_wb_info > MAX_DWB_PIPES) {

drivers/gpu/drm/amd/display/dc/dc_stream.h

267

struct dc_writeback_info writeback_info[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/dc_stream.h

82

struct dc_writeback_info writeback_info[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2548

ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2573

ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

439

ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

562

ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

266

struct dwbc *dwbc[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

267

struct mcif_wb *mcif_wb[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

572

struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1649

for (j = 0; j < MAX_DWB_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1676

if (dwb_pipe >= MAX_DWB_PIPES)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1550

for (j = 0; j < MAX_DWB_PIPES; j++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1577

if (dwb_pipe >= MAX_DWB_PIPES)