arch/x86/events/intel/uncore_nhmex.c

531

MBOX_INC_SEL_EXTAR_REG(0x0, DSP),

arch/x86/events/intel/uncore_nhmex.c

532

MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),

arch/x86/events/intel/uncore_nhmex.c

533

MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),

arch/x86/events/intel/uncore_nhmex.c

534

MBOX_INC_SEL_EXTAR_REG(0x9, ISS),

arch/x86/events/intel/uncore_nhmex.c

536

MBOX_INC_SEL_EXTAR_REG(0xa, ISS),

arch/x86/events/intel/uncore_nhmex.c

537

MBOX_INC_SEL_EXTAR_REG(0xa, PLD),

arch/x86/events/intel/uncore_nhmex.c

538

MBOX_INC_SEL_EXTAR_REG(0xb, PLD),

arch/x86/events/intel/uncore_nhmex.c

540

MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),

arch/x86/events/intel/uncore_nhmex.c

541

MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),

arch/x86/events/intel/uncore_nhmex.c

542

MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),

arch/x86/events/intel/uncore_nhmex.c

543

MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),

arch/x86/events/intel/uncore_nhmex.c

544

MBOX_INC_SEL_EXTAR_REG(0x16, PGT),