AR_PHY_AIC_CTRL_0_B1
REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,
REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1,
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);