drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10977

dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3356

struct dc_surface_update surface_updates[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3357

struct dc_plane_info plane_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3358

struct dc_scaling_info scaling_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3359

struct dc_flip_addrs flip_addrs[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9942

struct dc_surface_update surface_updates[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9943

struct dc_plane_info plane_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9944

struct dc_scaling_info scaling_infos[MAX_SURFACES];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9945

struct dc_flip_addrs flip_addrs[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/core/dc.c

3595

struct dc_plane_state *new_planes[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

4856

struct dc_surface_update srf_updates[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

5221

struct dc_fast_update fast_update[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

5307

struct dc_fast_update fast_update[MAX_SURFACES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc.c

7208

struct dc_surface_update intermediate_updates[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/core/dc.c

7301

struct dc_fast_update fast_update[MAX_SURFACES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_state.c

481

} else if (stream_status->plane_count == MAX_SURFACES) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

483

plane_state, MAX_SURFACES);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

598

struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };

drivers/gpu/drm/amd/display/dc/core/dc_state.c

877

struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };

drivers/gpu/drm/amd/display/dc/dc.h

1575

struct dc_plane_state plane_states[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/dc.h

1933

struct dc_plane_state *plane_states[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/dc_stream.h

61

struct dc_plane_state *plane_states[MAX_SURFACES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

815

struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };