Symbol: MAX_POST_DIVR_FREQ
drivers/clk/analogbits/wrpll-cln28hpc.c
200
c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
drivers/clk/analogbits/wrpll-cln28hpc.c
87
post_divr_freq > MAX_POST_DIVR_FREQ) {