drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

646

static_assert(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

570

static_assert(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

566

static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

692

if (i > MAX_NUM_DPM_LVL - 1)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

693

i = MAX_NUM_DPM_LVL - 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

493

static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1107

if (i > MAX_NUM_DPM_LVL - 1)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1108

i = MAX_NUM_DPM_LVL - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

223

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

312

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

219

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

318

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2676

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2822

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3166

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3261

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

364

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

721

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

811

if (num_states > MAX_NUM_DPM_LVL) {

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

143

struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2158

for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

115

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

138

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

161

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

184

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

46

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

69

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

92

for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {