drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1334

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1350

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1366

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1382

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1398

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1413

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1425

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1438

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1453

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1470

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1487

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1505

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1524

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1542

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1559

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1575

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1589

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1602

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1617

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1633

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1650

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1678

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1697

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1713

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1728

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1742

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drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1758

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1771

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1784

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1801

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1819

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1837

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1851

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1867

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1882

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1896

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1911

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1928

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3152

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3164

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3176

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3188

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3200

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3210

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3220

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3232

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3242

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3253

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3272

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3295

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3316

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3336

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3351

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3364

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3377

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3389

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3402

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3415

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3426

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3436

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3448

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3461

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3473

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3484

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3495

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3508

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3522

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3535

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3547

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3559

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3572

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3585

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3598

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3610

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3622

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3635

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3647

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3660

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3674

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3688

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3702

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3714

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3724

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3734

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3745

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3759

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3772

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3784

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3797

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3811

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3828

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3843

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3855

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3868

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3887

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3904

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3916

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3929

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3942

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3955

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3967

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3979

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3991

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4006

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4020

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4031

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4042

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4054

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4067

if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

733

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

943

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1369

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1375

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/inc/core_types.h

663

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE];