AR_PHY_GLB_CONTROL
REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1);
REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0);
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,