drivers/clk/tegra/clk-dfll.c

1353

for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)

drivers/clk/tegra/clk-dfll.c

1649

u8 lut_bottom = MAX_DFLL_VOLTAGES;

drivers/clk/tegra/clk-dfll.c

1652

for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {

drivers/clk/tegra/clk-dfll.c

1661

if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))

drivers/clk/tegra/clk-dfll.c

1667

if ((lut_bottom == MAX_DFLL_VOLTAGES) ||

drivers/clk/tegra/clk-dfll.c

1727

v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));

drivers/clk/tegra/clk-dfll.c

1738

v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;

drivers/clk/tegra/clk-dfll.c

1856

for (i = 0; i < MAX_DFLL_VOLTAGES; i++)

drivers/clk/tegra/clk-dfll.c

1872

td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);

drivers/clk/tegra/clk-dfll.c

303

unsigned lut[MAX_DFLL_VOLTAGES];

drivers/clk/tegra/clk-dfll.c

304

unsigned long lut_uv[MAX_DFLL_VOLTAGES];

drivers/clk/tegra/clk-dfll.c

681

for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {