MAX_CHIP_IDS
block_id * MAX_CHIP_IDS + dev_data->chip_id;
reset_reg_id * MAX_CHIP_IDS + dev_data->chip_id;
u32 reset_val[MAX_CHIP_IDS];
enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
u32 cm_ctx_lid_sizes[MAX_CHIP_IDS][NUM_CM_CTX_TYPES];
bool exists[MAX_CHIP_IDS];
u32 default_val[MAX_CHIP_IDS];
u32 crash_preset_val[MAX_CHIP_IDS];
u32 num_entries[MAX_CHIP_IDS];
u32 is_256b_bit_offset[MAX_CHIP_IDS];
u32 ram_size[MAX_CHIP_IDS]; /* In dwords */
static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
} qed_iwarp_rcv_wnd_size[MAX_CHIP_IDS] = {