MASK_24
priv->bank_bit[0] = FIELD_GET(MASK_24, regval);
priv->lrank_bit[2] = FIELD_GET(MASK_24, regval);
priv->col_bit[0] = FIELD_GET(MASK_24, regval);
col_bit_0 = FIELD_GET(MASK_24, error_data[ADEC9]);
err_addr |= (pinf.bank & BIT(0)) << FIELD_GET(MASK_24, reg);
err_addr |= (pinf.lrank & BIT(0)) << FIELD_GET(MASK_24, reg);
saa7146_write(dev, MC1, (MASK_08 | MASK_24));
saa7146_write(dev, MC2, (MASK_08|MASK_24));
saa7146_write(dev, MC1, (MASK_08 | MASK_24 | MASK_10 | MASK_26));
saa7146_write(dev, MC1, (MASK_08 | MASK_24 | MASK_10 | MASK_26));
saa7146_write(dev, MC2, (MASK_08 | MASK_24));
1 * (MASK_08 | MASK_24) | // BRS control
saa7146_write(dev, MC2, MASK_08 | MASK_24);
#define CMD_SIG3 MASK_24