MASK_06
saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
WRITE_RPS0(MASK_06 | MASK_22); /* => mask */
WRITE_RPS0(MASK_06 | MASK_22); /* => values */
WRITE_RPS0(MASK_22 | MASK_06); /* => mask */
saa7146_write(dev, MC2, MASK_22 | MASK_06);
saa7146_write(dev, MC2, MASK_22 | MASK_06);
saa7146_write(dev, MC2, MASK_22 | MASK_06);
if (saa7146_read(saa, PSR) & MASK_06) {
.irq_mask = MASK_03 | MASK_06 | MASK_10,
SAA7146_IER_ENABLE(saa, MASK_06);
SAA7146_IER_DISABLE(saa, MASK_06);
if (*isr & MASK_06)
0 * (MASK_06 | MASK_22) | // HPS_CTRL1