MASKLWORD
reg_hp_tx = u32tmp & MASKLWORD;
reg_lp_tx = u32tmp & MASKLWORD;
reg_hp_tx = u32tmp & MASKLWORD;
reg_lp_tx = u32tmp & MASKLWORD;
reg_hp_tx = u32tmp & MASKLWORD;
reg_lp_tx = u32tmp & MASKLWORD;
reg_hp_tx = u4_tmp & MASKLWORD;
reg_lp_tx = u4_tmp & MASKLWORD;
reg_hp_tx = u4tmp & MASKLWORD;
reg_lp_tx = u4tmp & MASKLWORD;
rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
MASKLWORD, 0);
MASKLWORD, value32);
MASKLWORD, value32);
rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
reg_hp_tx = u32_tmp & MASKLWORD;
reg_lp_tx = u32_tmp & MASKLWORD;
rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
coex_stat->hi_pri_tx = FIELD_GET(MASKLWORD, tmp);
coex_stat->lo_pri_tx = FIELD_GET(MASKLWORD, tmp);
rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD);
{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
hal->ch_param[1] & MASKLWORD);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
hal->ch_param[1] & MASKLWORD);
rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
mask = MASKLWORD;
dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD);
rtw_write32_mask(rtwdev, REG_TXPSEL, MASKLWORD, 0x1111);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, 0x4010, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, 0x4010, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, 0x0, mac_idx);
rtwdev, R_RPT_COM, MASKLWORD);
val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD) -
rtwdev, 0x80fc, MASKLWORD);
val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
rtwdev, R_RPT_COM, MASKLWORD);
val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN, MASKLWORD, 0x0000);
rtw89_phy_write32_mask(rtwdev, R_P1_TXAGC_TH, MASKLWORD, 0x0000);
tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);