MASKBYTE2
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2,
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
MASKBYTE2, power_index);
rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
{.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80
u32_encode_bits(i + 2, MASKBYTE2) |
pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
MASKBYTE2);
MASKBYTE2);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
MASKBYTE2);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
MASKBYTE2);
rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), MASKBYTE2);