AR_CFG
REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
mask = REG_READ(ah, AR_CFG);
REG_WRITE(ah, AR_CFG, mask);
REG_READ(ah, AR_CFG));
REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);