drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

217

#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

218

#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

219

#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

220

#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

221

#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

222

#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

223

#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

224

#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

225

#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

226

#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

227

#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

228

#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

229

#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

230

#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)

drivers/net/ethernet/chelsio/cxgb/fpga_defs.h

231

#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)