ARM_SMMU_CR0
ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK);
reg = readl_relaxed(smmu->base + ARM_SMMU_CR0);
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,