drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1025

else if (mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1043

CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1137

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

509

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

534

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

537

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

540

dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

542

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

551

next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

602

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

946

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

949

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

951

dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

953

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

961

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

985

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1244

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1247

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1249

dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1251

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1259

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1284

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1324

else if (mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1342

CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1440

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

63

s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

801

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

82

s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

828

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

833

dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

835

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

845

CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

896

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

239

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

242

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

245

dpp3_configure_gamcor_lut(dpp_base, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

300

next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

303

REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

69

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

161

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

252

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

255

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

257

dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

259

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

267

REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

307

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

425

next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

448

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

451

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

454

mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

456

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

467

next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1242

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

149

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

363

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

364

else if (current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

367

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

370

mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

372

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

382

MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

459

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

882

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

885

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

887

mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

889

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

897

REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

916

else if (mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

947

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

980

MPC_RMU_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

113

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

279

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

284

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

286

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

296

MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

314

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

731

if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

734

next_mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

736

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

738

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

746

REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

774

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

808

MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

897

else if (mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

932

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

123

const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

142

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

144

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

159

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

161

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

97

mode = LUT_RAM_A;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

173

const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

181

mpc42_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

183

if (next_mode == LUT_RAM_A)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

625

const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

633

mpc42_configure_rmcm_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

635

if (next_mode == LUT_RAM_A)