MA35_NFI_REG_NANDCTL
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg & ~DISABLE_CS0, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);
readl(nand->regs + MA35_NFI_REG_NANDCTL) & BCH_MASK);
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_W_EN,
nand->regs + MA35_NFI_REG_NANDCTL);
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_R_EN,
nand->regs + MA35_NFI_REG_NANDCTL);
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | SWRST,
nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK);
writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL);
writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL);