drivers/gpu/drm/i915/gt/intel_workarounds.c

2833

wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2855

wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2858

wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2866

wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,

drivers/gpu/drm/xe/xe_wa.c

264

SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS))

drivers/gpu/drm/xe/xe_wa.c

357

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))

drivers/gpu/drm/xe/xe_wa.c

367

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))

drivers/gpu/drm/xe/xe_wa.c

429

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,

drivers/gpu/drm/xe/xe_wa.c

444

XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,

drivers/gpu/drm/xe/xe_wa.c

461

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))

drivers/gpu/drm/xe/xe_wa.c

466

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))

drivers/gpu/drm/xe/xe_wa.c

592

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))

drivers/gpu/drm/xe/xe_wa.c

597

XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))