M2
/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
/*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
/*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
/*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
/*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
/*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
/*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
/*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
/*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
/*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
/*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
/*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
/*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
/*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
/*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
/*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
/*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
/*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
/*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
/*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
/*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
/*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
/*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
/*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
/*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
/*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
/*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
/*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
/*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
/*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
/*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
rsr.M2 \at1 // MAC16 option
wsr.M2 \at1 // MAC16 option
rsr \at1, M2
wsr \at1, M2
rsr \at1, M2 // MAC16 option
wsr \at1, M2 // MAC16 option
wsr.M2 \at1 // MAC16 option
rsr.M2 \at1 // MAC16 option
rsr.M2 \at1 // MAC16 option
wsr.M2 \at1 // MAC16 option
rsr.M2 \at1 // MAC16 option
wsr.M2 \at1 // MAC16 option
mhi_state(M2, "M2") \
seq_printf(m, "M0: %u M2: %u M3: %u", mhi_cntrl->M0, mhi_cntrl->M2,
mhi_pm_state(M2, "M2") \
mhi_cntrl->M2++;
pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
pllvals->N2 = pllvals->M2 = 1;
pllvals->M2 = (pll1 >> 4) & 0x7;
if (!pv->M1 || !pv->M2)
return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
uint8_t M1, N1, M2, N2;
uint8_t N1, M1, N2, M2;
int N1, M1, N2, M2, P;
int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
pv->M2 = M2;
int *N1, int *M1, int *N2, int *M2, int *log2P)
ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
int N1, M1, N2, M2, log2P;
&N1, &M1, &N2, &M2, &log2P);
if (N2 == M2) {
clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
int M2 = (coef & 0x00ff0000) >> 16;
if (M2)
khz = khz * N2 / M2;
int N1, N2, M1, M2;
M2 = (coef & 0x00ff0000) >> 16;
if (M2)
freq = freq * N2 / M2;
int *N1, int *M1, int *N2, int *M2, int *P);
int M1, N1, M2, N2, log2P;
for (M2 = minM2; M2 <= maxM2; M2++) {
if (calcclk1/M2 < minU2)
if (calcclk1/M2 > maxU2)
N2 = (clkP * M2 + calcclk1/2) / calcclk1;
if (N2/M2 < 4 || N2/M2 > 10)
calcclk2 = calcclk1 * N2 / M2;
*pM2 = M2;
int *N1, int *M1, int *N2, int *M2, int *P)
*M2 = 1;
ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
(pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
int N1, M1, N2, M2, P;
ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
pv.M2 = M2;
int N1, M1, N2, M2, P;
ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
(M2 << 16) | N2);
&ram->N2, &ram->M2, &ram->P2);
int N2, M2, P2;
const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
int *N2, int *M2, int *P2)
*M2 = 1;
int N1, M1, N2, M2;
ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
if (N2 == M2) {
ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
int N1, M1, N2, M2, P;
&N1, &M1, &N2, &M2, &P);
SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8);
PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8));
FUNC_GROUP_DECL(ADC8, M2);
ASPEED_PINCTRL_PIN(M2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
u32 M0, M2, M3;
stats->M2 += delta*(val - stats->mean);
variance = stats->M2 / (stats->n - 1);
stats->M2 = 0.0;
double n, mean, M2;