M10V_PLL7DIV2
{M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1},
{M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1},
{M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1},
{M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1},
{M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1},
{M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1},
{M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1},