M10V_PLL10DIV2
{M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1},
{M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1},
{M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1},
hw = m10v_clk_hw_register_divider(NULL, "rclk", M10V_PLL10DIV2, 0,