arch/xtensa/variants/csp/include/variant/tie-asm.h

109

rsr.M1 \at1 // MAC16 option

arch/xtensa/variants/csp/include/variant/tie-asm.h

176

wsr.M1 \at1 // MAC16 option

arch/xtensa/variants/dc232b/include/variant/tie-asm.h

50

rsr \at2, M1

arch/xtensa/variants/dc232b/include/variant/tie-asm.h

93

wsr \at2, M1

arch/xtensa/variants/dc233c/include/variant/tie-asm.h

106

rsr \at1, M1 // MAC16 option

arch/xtensa/variants/dc233c/include/variant/tie-asm.h

171

wsr \at1, M1 // MAC16 option

arch/xtensa/variants/de212/include/variant/tie-asm.h

152

wsr.M1 \at1 // MAC16 option

arch/xtensa/variants/de212/include/variant/tie-asm.h

97

rsr.M1 \at1 // MAC16 option

arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h

109

rsr.M1 \at1 // MAC16 option

arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h

176

wsr.M1 \at1 // MAC16 option

arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h

106

rsr.M1 \at1 // MAC16 option

arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h

173

wsr.M1 \at1 // MAC16 option

drivers/bus/mhi/common.h

304

mhi_state(M1, "M1") \

drivers/gpu/drm/nouveau/dispnv04/crtc.c

166

pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

169

pv->N1, pv->M1, pv->log2P);

drivers/gpu/drm/nouveau/dispnv04/hw.c

153

pllvals->M1 &= 0xf; /* only 4 bits */

drivers/gpu/drm/nouveau/dispnv04/hw.c

208

if (!pv->M1 || !pv->M2)

drivers/gpu/drm/nouveau/dispnv04/hw.c

211

return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;

drivers/gpu/drm/nouveau/dispnv04/hw.c

271

if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&

drivers/gpu/drm/nouveau/dispnv04/hw.c

279

pv.M1 = pll_lim.vco1.max_m;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h

11

uint8_t M1, N1, M2, N2;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h

9

uint8_t N1, M1, N2, M2;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

57

int N1, M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

71

M1 = (coef & 0x000000ff);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

72

if ((ctrl & 0x80000000) && M1) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

73

clock = ref * N1 / M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c

35

int N1, M1, N2, M2, P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c

36

int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c

40

pv->M1 = M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

125

int *N1, int *M1, int *N2, int *M2, int *log2P)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

138

ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

151

int N1, M1, N2, M2, log2P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

156

&N1, &M1, &N2, &M2, &log2P);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

162

clk->npll_coef = (N1 << 8) | M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

165

clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

171

&N1, &M1, NULL, NULL, &log2P);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

175

clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

64

int M1 = (coef & 0x000000ff) >> 0;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

68

if ((ctrl & 0x80000000) && M1) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c

69

khz = ref * N1 / M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

166

int N1, N2, M1, M2;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

177

M1 = (coef & 0x000000ff);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

178

if ((ctrl & 0x80000000) && M1) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

179

freq = ref * N1 / M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h

9

int *N1, int *M1, int *N2, int *M2, int *P);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

151

int M1, N1, M2, N2, log2P;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

164

for (M1 = minM1; M1 <= maxM1; M1++) {

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

165

if (crystal/M1 < minU1)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

167

if (crystal/M1 > maxU1)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

171

calcclk1 = crystal * N1 / M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

212

*pM1 = M1;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

228

int *N1, int *M1, int *N2, int *M2, int *P)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

233

ret = getMNP_single(subdev, info, freq, N1, M1, P);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c

239

ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

164

if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

363

int N1, M1, N2, M2, P;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

370

ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

376

pv.M1 = M1;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c

41

int N1, M1, N2, M2, P;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c

50

ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c

60

nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c

69

nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c

73

nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

143

int N1, M1, P;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

216

&N1, NULL, &M1, &P);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

225

ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

231

&N1, NULL, &M1, &P);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

238

ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

1033

*fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

1066

&ram->N1, &ram->fN1, &ram->M1, &ram->P1,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

1078

&ram->fN1, &ram->M1, &ram->P1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

133

int N1, fN1, M1, P1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

161

const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

703

const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

989

int *N1, int *fN1, int *M1, int *P1,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

995

*M1 = 1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

40

int N1, M1, N2, M2;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

49

ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

57

ram->coef = (N1 << 8) | M1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

60

ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

230

int N1, M1, N2, M2, P;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

331

&N1, &M1, &N2, &M2, &P);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

355

ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1518

SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1519

SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1520

PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9));

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

1521

FUNC_GROUP_DECL(ADC9, M1);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

2055

ASPEED_PINCTRL_PIN(M1),

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

2508

ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

2509

ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),