drivers/gpu/drm/gma500/cdv_device.c

258

regs->cdv.saveLVDS = REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_device.c

330

REG_WRITE(LVDS, regs->cdv.saveLVDS);

drivers/gpu/drm/gma500/cdv_intel_display.c

705

if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)

drivers/gpu/drm/gma500/cdv_intel_display.c

736

u32 lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_intel_display.c

755

REG_WRITE(LVDS, lvds);

drivers/gpu/drm/gma500/cdv_intel_display.c

756

REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_intel_display.c

855

is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

613

lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/gma_display.c

761

(REG_READ(LVDS) & LVDS_PORT_EN) != 0) {

drivers/gpu/drm/gma500/gma_display.c

768

if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==

drivers/gpu/drm/gma500/oaktrail_device.c

180

regs->psb.saveLVDS = PSB_RVDC32(LVDS);

drivers/gpu/drm/gma500/oaktrail_device.c

304

PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/

drivers/gpu/drm/gma500/oaktrail_lvds.c

102

lvds_port = (REG_READ(LVDS) &

drivers/gpu/drm/gma500/oaktrail_lvds.c

112

REG_WRITE(LVDS, lvds_port);

drivers/gpu/drm/gma500/psb_intel_display.c

231

u32 lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_display.c

251

REG_WRITE(LVDS, lvds);

drivers/gpu/drm/gma500/psb_intel_display.c

252

REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_display.c

323

is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);

drivers/gpu/drm/gma500/psb_intel_lvds.c

264

lvds_priv->saveLVDS = REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

317

REG_WRITE(LVDS, lvds_priv->saveLVDS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

761

lvds = REG_READ(LVDS);

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

62

OUTPUT_TYPE(LVDS),

drivers/gpu/drm/i915/display/intel_dpll.c

481

intel_lvds_port_enabled(display, LVDS, &lvds_pipe) &&

drivers/gpu/drm/i915/display/intel_dpll.c

483

u32 lvds = intel_de_read(display, LVDS);

drivers/gpu/drm/i915/display/intel_lvds.c

869

lvds_reg = LVDS;

drivers/gpu/drm/i915/display/intel_pps.c

1863

intel_lvds_port_enabled(display, LVDS, &panel_pipe);

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

276

case 0: state->proto = LVDS; state->link = 1; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

312

case 0: state->proto = LVDS; state->link = 1; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c

192

case 0: state->proto = LVDS; state->link = 1; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1052

if (ior->asy.proto == LVDS) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

1286

if (outp && ior->type == SOR && ior->asy.proto == LVDS) {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

239

case 0: state->proto = LVDS; state->link = 1; break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

70

case DCB_OUTPUT_LVDS : *type = SOR; return LVDS;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

405

if (ior->arm.proto != LVDS)

drivers/video/fbdev/nvidia/nv_setup.c

634

par->LVDS = 0;

drivers/video/fbdev/nvidia/nv_setup.c

638

par->LVDS = 1;

drivers/video/fbdev/nvidia/nv_setup.c

639

printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");

drivers/video/fbdev/nvidia/nv_type.h

135

int LVDS;