arch/mips/lantiq/xway/dma.c

103

ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

115

ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

135

ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

137

ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

138

while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)

arch/mips/lantiq/xway/dma.c

153

ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

168

ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

267

ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

269

ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);