arch/powerpc/platforms/cell/spufs/spu_restore.c

110

offset = LSCSA_QW_OFFSET(ppuint_mb);

arch/powerpc/platforms/cell/spufs/spu_restore.c

124

offset = LSCSA_QW_OFFSET(fpcr);

arch/powerpc/platforms/cell/spufs/spu_restore.c

137

offset = LSCSA_QW_OFFSET(srr0);

arch/powerpc/platforms/cell/spufs/spu_restore.c

150

offset = LSCSA_QW_OFFSET(event_mask);

arch/powerpc/platforms/cell/spufs/spu_restore.c

163

offset = LSCSA_QW_OFFSET(tag_mask);

arch/powerpc/platforms/cell/spufs/spu_restore.c

191

offset = LSCSA_QW_OFFSET(stopped_status);

arch/powerpc/platforms/cell/spufs/spu_restore.c

78

offset = LSCSA_QW_OFFSET(decr_status);

arch/powerpc/platforms/cell/spufs/spu_restore.c

81

offset = LSCSA_QW_OFFSET(decr);

arch/powerpc/platforms/cell/spufs/spu_restore.c

96

offset = LSCSA_QW_OFFSET(ppu_mb);

arch/powerpc/platforms/cell/spufs/spu_save.c

100

offset = LSCSA_QW_OFFSET(srr0);

arch/powerpc/platforms/cell/spufs/spu_save.c

32

offset = LSCSA_QW_OFFSET(event_mask);

arch/powerpc/platforms/cell/spufs/spu_save.c

43

offset = LSCSA_QW_OFFSET(tag_mask);

arch/powerpc/platforms/cell/spufs/spu_save.c

76

offset = LSCSA_QW_OFFSET(fpcr);

arch/powerpc/platforms/cell/spufs/spu_save.c

88

offset = LSCSA_QW_OFFSET(decr);