drivers/gpu/drm/i915/gt/intel_context_sseu.c

28

LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4;

drivers/gpu/drm/i915/gt/intel_lrc.c

1009

ptr -= LRC_STATE_OFFSET; /* back to start of context image */

drivers/gpu/drm/i915/gt/intel_lrc.c

1041

__lrc_init_regs(state + LRC_STATE_OFFSET, ce, engine, inhibit);

drivers/gpu/drm/i915/gt/intel_lrc.c

1215

ce->lrc_reg_state = vaddr + LRC_STATE_OFFSET;

drivers/gpu/drm/i915/gt/intel_lrc.c

1230

check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,

drivers/gpu/drm/i915/gt/intel_lrc.c

1268

*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +

drivers/gpu/drm/i915/gt/intel_lrc.c

1296

*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +

drivers/gpu/drm/i915/gt/intel_lrc.c

1312

*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +

drivers/gpu/drm/i915/gt/selftest_lrc.c

1169

hw += LRC_STATE_OFFSET / sizeof(*hw);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1311

lrc += LRC_STATE_OFFSET / sizeof(*hw);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1322

hw += LRC_STATE_OFFSET / sizeof(*hw);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1635

LRC_STATE_OFFSET + context_wa_bb_offset(ce) +

drivers/gpu/drm/i915/gt/selftest_lrc.c

1782

LRC_STATE_OFFSET);

drivers/gpu/drm/i915/gt/selftest_lrc.c

187

hw += LRC_STATE_OFFSET / sizeof(*hw);

drivers/gpu/drm/i915/gt/selftest_lrc.c

381

hw += LRC_STATE_OFFSET / sizeof(*hw);

drivers/gpu/drm/i915/gt/selftest_lrc.c

999

hw += LRC_STATE_OFFSET / sizeof(*hw);

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

477

LRC_STATE_OFFSET) / sizeof(u32)));

drivers/gpu/drm/i915/i915_perf.c

2494

offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;