arch/arc/kernel/perf_event.c

109

[C(LL)] = {

arch/arm/nwfpe/ARM-gcc.h

62

#define LIT64( a ) a##LL

arch/csky/kernel/perf_event.c

773

[C(LL)] = {

arch/loongarch/kernel/perf_event.c

717

[C(LL)] = {

arch/mips/include/asm/addrspace.h

30

#define _CONST64_(x) x ## LL

arch/mips/kernel/perf_event_mipsxx.c

1042

[C(LL)] = {

arch/mips/kernel/perf_event_mipsxx.c

1123

[C(LL)] = {

arch/mips/kernel/perf_event_mipsxx.c

1283

[C(LL)] = {

arch/mips/kernel/perf_event_mipsxx.c

1345

[C(LL)] = {

arch/mips/kernel/perf_event_mipsxx.c

1409

[C(LL)] = {

arch/mips/kernel/traps.c

619

if ((opcode & OPCODE) == LL) {

arch/powerpc/perf/e500-pmu.c

55

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/powerpc/perf/e6500-pmu.c

53

[C(LL)] = {

arch/powerpc/perf/generic-compat-pmu.c

214

[ C(LL) ] = {

arch/powerpc/perf/mpc7450-pmu.c

376

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/powerpc/perf/power10-pmu.c

387

[C(LL)] = {

arch/powerpc/perf/power10-pmu.c

488

[C(LL)] = {

arch/powerpc/perf/power5+-pmu.c

636

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/powerpc/perf/power5-pmu.c

578

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/powerpc/perf/power6-pmu.c

510

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/powerpc/perf/power7-pmu.c

350

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/powerpc/perf/power8-pmu.c

295

[ C(LL) ] = {

arch/powerpc/perf/power9-pmu.c

366

[ C(LL) ] = {

arch/powerpc/perf/ppc970-pmu.c

449

[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */

arch/sh/kernel/cpu/sh4/perf_event.c

121

[ C(LL) ] = {

arch/sh/kernel/cpu/sh4/softfloat.c

42

#define LIT64( a ) a##LL

arch/sh/kernel/cpu/sh4a/perf_event.c

146

[ C(LL) ] = {

arch/sparc/kernel/perf_event.c

249

[C(LL)] = {

arch/sparc/kernel/perf_event.c

387

[C(LL)] = {

arch/sparc/kernel/perf_event.c

522

[C(LL)] = {

arch/sparc/kernel/perf_event.c

659

[C(LL)] = {

arch/x86/events/amd/core.c

167

[C(LL)] = {

arch/x86/events/amd/core.c

63

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1063

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1140

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1185

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1263

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1326

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1482

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1559

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1634

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1754

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1817

[ C(LL ) ] = {

arch/x86/events/intel/core.c

1932

[ C(LL ) ] = {

arch/x86/events/intel/core.c

2023

[ C(LL ) ] = {

arch/x86/events/intel/core.c

2125

[ C(LL ) ] = {

arch/x86/events/intel/core.c

2174

[ C(LL ) ] = {

arch/x86/events/intel/core.c

2308

[C(LL)] = {

arch/x86/events/intel/core.c

2370

[C(LL)] = {

arch/x86/events/intel/core.c

2424

[C(LL)] = {

arch/x86/events/intel/core.c

2486

[C(LL)] = {

arch/x86/events/intel/core.c

2518

[C(LL)] = {

arch/x86/events/intel/core.c

2542

[C(LL)] = {

arch/x86/events/intel/core.c

2558

[C(LL)] = {

arch/x86/events/intel/core.c

2574

[C(LL)] = {

arch/x86/events/intel/core.c

2590

[C(LL)] = {

arch/x86/events/intel/core.c

2606

[C(LL)] = {

arch/x86/events/intel/core.c

2723

[C(LL)] = {

arch/x86/events/intel/core.c

667

[ C(LL ) ] = {

arch/x86/events/intel/core.c

747

[ C(LL ) ] = {

arch/x86/events/intel/core.c

802

[ C(LL ) ] = {

arch/x86/events/intel/core.c

826

[ C(LL ) ] = {

arch/x86/events/intel/core.c

8345

hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |

arch/x86/events/intel/core.c

8347

hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|

arch/x86/events/intel/core.c

843

[ C(LL ) ] = {

arch/x86/events/intel/core.c

861

[ C(LL ) ] = {

arch/x86/events/intel/core.c

896

[ C(LL ) ] = {

arch/x86/events/intel/core.c

957

[ C(LL ) ] = {

arch/x86/events/intel/core.c

974

[ C(LL ) ] = {

arch/x86/events/intel/knc.c

60

[ C(LL ) ] = {

arch/x86/events/intel/p4.c

528

[ C(LL ) ] = {

arch/x86/events/intel/p6.c

59

[ C(LL ) ] = {

arch/x86/events/zhaoxin/core.c

185

[C(LL)] = {

arch/x86/events/zhaoxin/core.c

81

[C(LL)] = {

drivers/edac/mce_amd.c

152

u8 ll = LL(ec);

drivers/edac/mce_amd.c

167

if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {

drivers/edac/mce_amd.c

191

if (TT(ec) != TT_DATA || LL(ec) != LL_L1)

drivers/edac/mce_amd.c

211

if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)

drivers/edac/mce_amd.c

312

u8 ll = LL(ec);

drivers/edac/mce_amd.h

24

#define LL_MSG(x) ll_msgs[LL(x)]

drivers/net/ethernet/apm/xgene/xgene_enet_main.c

540

raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |

drivers/perf/arm_pmuv3.c

74

[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,

drivers/perf/arm_pmuv3.c

75

[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,

drivers/perf/arm_v7_pmu.c

185

[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,

drivers/perf/arm_v7_pmu.c

186

[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,

drivers/perf/arm_v7_pmu.c

187

[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,

drivers/perf/arm_v7_pmu.c

188

[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,

drivers/perf/arm_v7_pmu.c

324

[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,

drivers/perf/arm_v7_pmu.c

325

[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,

drivers/perf/arm_v7_pmu.c

326

[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,

drivers/perf/arm_v7_pmu.c

327

[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,

drivers/perf/arm_v7_pmu.c

373

[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,

drivers/perf/arm_v7_pmu.c

374

[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,

drivers/perf/arm_v7_pmu.c

375

[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,

drivers/perf/arm_v7_pmu.c

376

[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,

drivers/perf/arm_v7_pmu.c

422

[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ,

drivers/perf/arm_v7_pmu.c

423

[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,

drivers/perf/arm_v7_pmu.c

424

[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE,

drivers/perf/arm_v7_pmu.c

425

[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,

drivers/perf/riscv_pmu_sbi.c

200

[C(LL)] = {

drivers/perf/riscv_pmu_sbi.c

203

C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},

drivers/perf/riscv_pmu_sbi.c

205

C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},

drivers/perf/riscv_pmu_sbi.c

209

C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},

drivers/perf/riscv_pmu_sbi.c

211

C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},

drivers/perf/riscv_pmu_sbi.c

215

C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},

drivers/perf/riscv_pmu_sbi.c

217

C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},

include/asm-generic/int-ll64.h

31

#define S64_C(x) x ## LL

net/ceph/crush/mapper.c

253

__u64 RH, LH, LL, xl64, result;

net/ceph/crush/mapper.c

285

LL = __LL_tbl[index2];

net/ceph/crush/mapper.c

287

LH = LH + LL;

tools/perf/util/evsel.c

891

[C(LL)] = (CACHE_READ | CACHE_WRITE | CACHE_PREFETCH),