LOCK_PREFIX
.macro LOCK_PREFIX
.macro LOCK_PREFIX
asm_inline volatile(LOCK_PREFIX "andl %1, %0"
asm_inline volatile(LOCK_PREFIX "orl %1, %0"
asm_inline volatile(LOCK_PREFIX "xorl %1, %0"
asm_inline volatile(LOCK_PREFIX "addl %1, %0"
asm_inline volatile(LOCK_PREFIX "subl %1, %0"
return GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, e, "er", i);
asm_inline volatile(LOCK_PREFIX "incl %0"
asm_inline volatile(LOCK_PREFIX "decl %0"
return GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, e);
return GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, e);
return GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, s, "er", i);
asm_inline volatile(LOCK_PREFIX "andq %1, %0"
asm_inline volatile(LOCK_PREFIX "orq %1, %0"
asm_inline volatile(LOCK_PREFIX "xorq %1, %0"
asm_inline volatile(LOCK_PREFIX "addq %1, %0"
asm_inline volatile(LOCK_PREFIX "subq %1, %0"
return GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, e, "er", i);
asm_inline volatile(LOCK_PREFIX "incq %0"
asm_inline volatile(LOCK_PREFIX "decq %0"
return GEN_UNARY_RMWcc(LOCK_PREFIX "decq", v->counter, e);
return GEN_UNARY_RMWcc(LOCK_PREFIX "incq", v->counter, e);
return GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, s, "er", i);
asm_inline volatile(LOCK_PREFIX "xorb %2,%1"
asm_inline volatile(LOCK_PREFIX "xorb %b1,%0"
asm_inline volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr);
return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr);
return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr);
asm_inline volatile(LOCK_PREFIX "orb %b1,%0"
asm_inline volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
asm_inline volatile(LOCK_PREFIX "andb %b1,%0"
asm_inline volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
__raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
__raw_try_cmpxchg((ptr), (pold), (new), (size), LOCK_PREFIX)
#define xadd(ptr, inc) __xadd((ptr), (inc), LOCK_PREFIX)
return __arch_cmpxchg64(ptr, old, new, LOCK_PREFIX);
return __arch_try_cmpxchg64(ptr, oldp, new, LOCK_PREFIX);
return __arch_cmpxchg128(ptr, old, new, LOCK_PREFIX);
return __arch_try_cmpxchg128(ptr, oldp, new, LOCK_PREFIX);
"3:\t" LOCK_PREFIX "cmpxchgl %3, %2\n" \
unsafe_atomic_op1(LOCK_PREFIX "xaddl %0, %2", oval, uaddr, oparg, Efault);
"1:\t" LOCK_PREFIX "cmpxchgl %3, %2\n"
val = GEN_BINARY_RMWcc(LOCK_PREFIX "btsl", lock->val.counter, c,
LOCK_PREFIX "cmpxchg %dl,(%rdi)\n\t" \
"1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\
"1: " LOCK_PREFIX "cmpxchg8b %[ptr]\n" \
"1: " LOCK_PREFIX "cmpxchg"itype" %[new], %[ptr]\n"\
"1: " LOCK_PREFIX "cmpxchg8b %[ptr]\n" \
asm volatile(LOCK_PREFIX "orq %0, %1\n"
LOCK_PREFIX "andq %0, %2\n"
asm volatile(LOCK_PREFIX "orl %0, %1\n"
LOCK_PREFIX "andl %0, %2\n"
asm volatile(LOCK_PREFIX "incl %0"
GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, "%0", "e");
GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, "Ir", nr, "%0", "c");
GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, "Ir", nr, "%0", "c");
__raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
__asm__ __volatile__(KVM_FEP LOCK_PREFIX "cmpxchg %[new], %[ptr]" \