arch/arm/mach-spear/time.c

133

writew(period, gpt_base + LOAD(CLKEVT));

arch/arm/mach-spear/time.c

162

writew(cycles, gpt_base + LOAD(CLKEVT));

arch/arm/mach-spear/time.c

81

writew(0xFFFF, gpt_base + LOAD(CLKSRC));

arch/arm64/net/bpf_jit.h

103

#define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)

arch/arm64/net/bpf_jit.h

61

#define A64_LDRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, LOAD)

arch/arm64/net/bpf_jit.h

64

#define A64_LDRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, LOAD)

arch/arm64/net/bpf_jit.h

67

#define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)

arch/arm64/net/bpf_jit.h

70

#define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)

arch/arm64/net/bpf_jit.h

78

#define A64_LDRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, LOAD)

arch/arm64/net/bpf_jit.h

81

#define A64_LDRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, LOAD)

arch/arm64/net/bpf_jit.h

84

#define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD)

arch/arm64/net/bpf_jit.h

87

#define A64_LDR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, LOAD)

arch/powerpc/include/asm/sstep.h

52

#define OP_IS_LOAD(type) ((LOAD <= (type) && (type) <= LOAD_VSX) || (type) == LARX)

arch/powerpc/include/asm/sstep.h

54

#define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX)

arch/powerpc/kvm/emulate_loadstore.c

103

case LOAD: {

arch/powerpc/lib/sstep.c

2332

op->type = MKOP(LOAD, u, 4);

arch/powerpc/lib/sstep.c

2337

op->type = MKOP(LOAD, u, 1);

arch/powerpc/lib/sstep.c

2390

op->type = MKOP(LOAD, u, 8);

arch/powerpc/lib/sstep.c

2411

op->type = MKOP(LOAD, u, 2);

arch/powerpc/lib/sstep.c

2417

op->type = MKOP(LOAD, SIGNEXT | u, 4);

arch/powerpc/lib/sstep.c

2423

op->type = MKOP(LOAD, SIGNEXT | u, 2);

arch/powerpc/lib/sstep.c

2433

op->type = MKOP(LOAD, BYTEREV, 8);

arch/powerpc/lib/sstep.c

2442

op->type = MKOP(LOAD, BYTEREV, 4);

arch/powerpc/lib/sstep.c

2520

op->type = MKOP(LOAD, BYTEREV, 2);

arch/powerpc/lib/sstep.c

2756

op->type = MKOP(LOAD, u, 4);

arch/powerpc/lib/sstep.c

2762

op->type = MKOP(LOAD, u, 1);

arch/powerpc/lib/sstep.c

2780

op->type = MKOP(LOAD, u, 2);

arch/powerpc/lib/sstep.c

2786

op->type = MKOP(LOAD, SIGNEXT | u, 2);

arch/powerpc/lib/sstep.c

2837

op->type = MKOP(LOAD, 0, 16);

arch/powerpc/lib/sstep.c

2876

op->type = MKOP(LOAD, 0, 8);

arch/powerpc/lib/sstep.c

2879

op->type = MKOP(LOAD, UPDATE, 8);

arch/powerpc/lib/sstep.c

2882

op->type = MKOP(LOAD, SIGNEXT, 4);

arch/powerpc/lib/sstep.c

2996

op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);

arch/powerpc/lib/sstep.c

3041

op->type = MKOP(LOAD, PREFIXED, 16);

arch/powerpc/lib/sstep.c

3044

op->type = MKOP(LOAD, PREFIXED, 8);

arch/powerpc/lib/sstep.c

3076

op->type = MKOP(LOAD, PREFIXED, 4);

arch/powerpc/lib/sstep.c

3079

op->type = MKOP(LOAD, PREFIXED, 1);

arch/powerpc/lib/sstep.c

3088

op->type = MKOP(LOAD, PREFIXED, 2);

arch/powerpc/lib/sstep.c

3091

op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);

arch/powerpc/lib/sstep.c

3119

case LOAD:

arch/powerpc/lib/sstep.c

3412

case LOAD:

arch/powerpc/lib/xor_vmx.c

108

LOAD(v1);

arch/powerpc/lib/xor_vmx.c

109

LOAD(v2);

arch/powerpc/lib/xor_vmx.c

110

LOAD(v3);

arch/powerpc/lib/xor_vmx.c

111

LOAD(v4);

arch/powerpc/lib/xor_vmx.c

139

LOAD(v1);

arch/powerpc/lib/xor_vmx.c

140

LOAD(v2);

arch/powerpc/lib/xor_vmx.c

141

LOAD(v3);

arch/powerpc/lib/xor_vmx.c

142

LOAD(v4);

arch/powerpc/lib/xor_vmx.c

143

LOAD(v5);

arch/powerpc/lib/xor_vmx.c

61

LOAD(v1);

arch/powerpc/lib/xor_vmx.c

62

LOAD(v2);

arch/powerpc/lib/xor_vmx.c

82

LOAD(v1);

arch/powerpc/lib/xor_vmx.c

83

LOAD(v2);

arch/powerpc/lib/xor_vmx.c

84

LOAD(v3);

arch/powerpc/perf/isa207-common.c

359

dsrc->val |= P(OP, LOAD);

arch/powerpc/perf/isa207-common.c

369

dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);

arch/sparc/lib/GENmemcpy.S

22

#ifndef LOAD

arch/sparc/lib/M7memcpy.S

116

#ifndef LOAD

arch/sparc/lib/NG2memcpy.S

50

#ifndef LOAD

arch/sparc/lib/NG4memcpy.S

65

#ifndef LOAD

arch/sparc/lib/NGmemcpy.S

38

#ifndef LOAD

arch/sparc/lib/U1memcpy.S

42

#ifndef LOAD

arch/sparc/lib/U3memcpy.S

40

#ifndef LOAD

arch/sparc/lib/csum_copy.S

27

#ifndef LOAD

arch/x86/events/intel/ds.c

119

#define OP_LH (P(OP, LOAD) | P(LVL, HIT))

arch/x86/events/intel/ds.c

126

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */

arch/x86/events/intel/ds.c

234

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */

arch/x86/events/intel/ds.c

249

P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM */

arch/x86/events/intel/ds.c

271

P(OP, LOAD) | P(LVL, NA) | LEVEL(NA) | P(SNOOP, NA), /* 0x00: non-cache access */

arch/x86/events/intel/ds.c

294

P(OP, LOAD) | P(LVL, NA) | LEVEL(NA) | P(SNOOP, NA), /* 0x00: non-cache access */

arch/x86/events/intel/ds.c

315

P(OP, LOAD) | P(LVL, NA) | LEVEL(NA) | P(SNOOP, NA), /* 0x00: invalid */

arch/x86/events/intel/ds.c

513

val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);

arch/x86/events/intel/ds.c

548

val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);

arch/x86/events/intel/ds.c

606

val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);

drivers/crypto/caam/desc_constr.h

289

APPEND_CMD_PTR(load, LOAD)

drivers/crypto/caam/desc_constr.h

332

APPEND_CMD_PTR_TO_IMM(load, LOAD);

drivers/crypto/caam/desc_constr.h

389

APPEND_CMD_RAW_IMM(load, LOAD, u32);

drivers/crypto/caam/desc_constr.h

406

APPEND_CMD_RAW_IMM2(load, LOAD, be, 32);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

613

cp_set (ctx, SWAP_DIRECTION, LOAD);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

201

cp_set (ctx, SWAP_DIRECTION, LOAD);

drivers/gpu/drm/xe/instructions/xe_alu_commands.h

67

#define CS_ALU_INSTR_LOAD(op1, op2) __CS_ALU_INSTR(LOAD, op1, op2)

drivers/pwm/pwm-stmpe.c

160

program[0] = LOAD | 0xff; /* LOAD 0xff */

drivers/pwm/pwm-stmpe.c

168

program[0] = LOAD | 0x00; /* LOAD 0x00 */

drivers/pwm/pwm-stmpe.c

198

program[0] = LOAD | value;

lib/zlib_dfltcc/dfltcc_inflate.h

26

LOAD(); \

lib/zlib_inflate/inflate.c

359

LOAD();

lib/zlib_inflate/inflate.c

583

LOAD();

sound/pci/ice1712/se.c

127

const unsigned int LOAD = 0x040000;

sound/pci/ice1712/se.c

128

const unsigned int ALL_MASK = (DATA | CLOCK | LOAD);

sound/pci/ice1712/se.c

155

bits |= LOAD;

tools/perf/util/intel-pt.c

2278

#define OP_LH (P(OP, LOAD) | P(LVL, HIT))

tools/perf/util/intel-pt.c

2288

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* L3 miss|SNP N/A */

tools/perf/util/intel-pt.c

2308

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* L3 miss|SNP N/A */

tools/perf/util/mem-events.c

668

if (op & P(OP, LOAD)) {

tools/testing/selftests/powerpc/mm/stack_expansion_ldst.c

123

type == LOAD ? "load" : "store", delta, stack_used, stack_high,

tools/testing/selftests/powerpc/mm/stack_expansion_ldst.c

147

type == LOAD ? "load" : "store", delta, stack_used,

tools/testing/selftests/powerpc/mm/stack_expansion_ldst.c

181

test_one_type(LOAD, page_size, rlimit.rlim_cur);