ARM
ARM( fpreg .req r11 )
ARM( "1: str" __t " " __reg_oper1 ", [%1], #4\n" ) \
ARM( "2: str" __t " " __reg_oper0 ", [%1]\n" ) \
.ARM.unwind_idx : { \
*(.ARM.exidx*) \
.ARM.unwind_tab : { \
*(.ARM.extab*) \
*(.ARM.exidx.exit.text) \
*(.ARM.extab.exit.text) \
*(.ARM.exidx.text.exit) \
*(.ARM.extab.text.exit) \
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) \
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) \
.ARM.attributes 0 : { *(.ARM.attributes) }
ARM( "1: "ins" %1, [%2], #1\n" ) \
ARM( "1: "ins" %1, [%2], #1\n" ) \
ARM( "1: "ins" %1, [%2], #1\n" ) \
ARM( "2: "ins" %1, [%2], #1\n" ) \
ARM( "3: "ins" %1, [%2], #1\n" ) \
ARM( "ldr r11, [sp], #4 \n\t" )
: "r0", "r2", "r3", "r4", "r5", "r6", ARM("r7") THUMB("r11"),
ARM( "stmdb sp!, {%[regs], r11} \n\t" )
LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
LPC32XX_CLK_DEFINE(ARM, "arm", CLK_IGNORE_UNUSED,
clk_set_parent(imx7ulp_clks[ARM].clk,
clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk);
clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
policy->clk = clks[ARM].clk;
old_freq = clk_get_rate(clks[ARM].clk) / 1000;
prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
if (!fourcc_mod_is_vendor(modifier, ARM)) {
IRQ_ENTRY(ARM),
WAKEUP_ENTRY(ARM)
saved_data = HINIC_SAVED_DATA_CLEAR(saved_data, ARM);
HINIC_SAVED_DATA_SET(1, ARM);
if (HINIC_SAVED_DATA_GET(saved_data, ARM)) {
fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))