drivers/gpu/drm/tilcdc/tilcdc_crtc.c

111

tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

117

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

123

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

131

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

133

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

145

tilcdc_set(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

161

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

353

reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

378

tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

434

tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

446

tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

475

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

698

if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

704

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

904

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

916

reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

918

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

920

tilcdc_set(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

943

tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,

drivers/gpu/drm/tilcdc/tilcdc_drv.c

154

REG(1, true, LCDC_RASTER_CTRL_REG),