drivers/gpu/drm/amd/display/dc/dc.h

1716

struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1469

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

284

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1112

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

623

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c

91

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

160

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

65

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

635

unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

803

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

224

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

54

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

82

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

163

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

180

const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1155

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

433

if (link->dpcd_caps.lttpr_caps.max_lane_count <= LANE_COUNT_DP_MAX)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1434

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1436

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

303

struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

347

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

356

const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

357

union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

361

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

598

union lane_status ln_status[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

600

union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

682

struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

693

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

751

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

856

const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

857

struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

862

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

113

const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

114

struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

161

const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

162

union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

83

union lane_status ln_status[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

85

union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

166

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

167

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

80

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

81

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

231

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

233

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

352

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

353

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

470

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

302

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

304

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

469

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

471

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

600

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

601

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

745

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

746

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

168

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

327

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

329

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

457

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

458

union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

46

union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX])

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

65

for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

74

const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.h

38

const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.h

43

union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]);

drivers/gpu/drm/amd/display/include/link_service_types.h

114

struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/include/link_service_types.h

115

union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX];