LCR
writel(0x83, UART1_REG(LCR));
writel(0x1b, UART1_REG(LCR));
writel(0x83, UART1_REG(LCR));
writel(0x1b, UART1_REG(LCR));
writel(0x83, UART1_REG(LCR));
writel(0x03, UART1_REG(LCR));
lcr = inb(port + LCR);
outb(lcr | DLAB, port + LCR);
outb(lcr, port + LCR);
outb(0x3, port + LCR); /* 8n1 */
c = inb(port + LCR);
outb(c | DLAB, port + LCR);
outb(c & ~DLAB, port + LCR);
static_call(serial_out)(early_serial_base, LCR, 0x3); /* 8n1 */
c = static_call(serial_in)(early_serial_base, LCR);
static_call(serial_out)(early_serial_base, LCR, c | DLAB);
static_call(serial_out)(early_serial_base, LCR, c & ~DLAB);
outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */
outb(0x01, LCR(dev->base_addr)); /* word length = 6 */
outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */
outb(0x01, LCR(dev->base_addr)); /* word length = 6 */
outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
outb(LCR_BIT5, LCR(iobase));
outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
outb(LCR_BIT8, LCR(dev->base_addr));
writel(0x83, UART1_REG(LCR));
writel(0x03, UART1_REG(LCR));
u8 LCR, val;
LCR = inb(base + UART_LCR);
outb(LCR, base + UART_LCR);
u8 LCR;
LCR = inb(base + UART_LCR);
outb(LCR, base + UART_LCR);
u8 LCR, val, qmcr;
LCR = inb(base + UART_LCR);
outb(LCR, base + UART_LCR);
u8 LCR, val;
LCR = inb(base + UART_LCR);
outb(LCR, base + UART_LCR);
u8 LCR, val;
LCR = inb(base + UART_LCR);
outb(LCR, base + UART_LCR);
lcr = LCR(conf_reg);
MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, LCR, LCR_DL_ENABLE);
MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, LCR,
regNum == LCR) {
status = send_cmd_write_uart_register(edge_port, LCR,