drivers/gpu/drm/i915/gt/intel_workarounds.c

709

wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

drivers/gpu/drm/i915/gt/intel_workarounds.c

710

REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));

drivers/gpu/drm/xe/xe_tuning.c

144

XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

drivers/gpu/drm/xe/xe_tuning.c

145

REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))

drivers/gpu/drm/xe/xe_tuning.c

163

XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

drivers/gpu/drm/xe/xe_tuning.c

164

REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))

drivers/gpu/drm/xe/xe_tuning.c

37

XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

drivers/gpu/drm/xe/xe_tuning.c

38

REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))

drivers/gpu/drm/xe/xe_tuning.c

42

XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

drivers/gpu/drm/xe/xe_tuning.c

43

REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))