LCD_SPU_SRAM_PARA1
base + LCD_SPU_SRAM_PARA1);
base + LCD_SPU_SRAM_PARA1);
para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
dcrtc->base + LCD_SPU_SRAM_PARA1);
CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
LCD_SPU_SRAM_PARA1);
LCD_SPU_SRAM_PARA1);
armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
0, LCD_SPU_SRAM_PARA1);
fbi->reg_base + LCD_SPU_SRAM_PARA1);