LCD_SPU_DMA_CTRL0
base + LCD_SPU_DMA_CTRL0);
armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0);
base + LCD_SPU_DMA_CTRL0);
armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0);
armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0);
armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0)
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0);