LCD_SPU_DMA_CTRL1
armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
LCD_SPU_DMA_CTRL1);
LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1)
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);
writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);