drivers/gpu/drm/tilcdc/tilcdc_crtc.c

326

reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

341

tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

364

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

367

tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

402

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

404

tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

407

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

409

tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

412

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

414

tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

417

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

419

tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

422

tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

424

tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);

drivers/gpu/drm/tilcdc/tilcdc_drv.c

421

REG(1, true, LCDC_RASTER_TIMING_2_REG),