Symbol: LCDC_RASTER_CTRL_REG
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
114
tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
120
tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
126
tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
134
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
136
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
148
tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
164
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
373
reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
399
tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
427
tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
429
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
464
tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
476
tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
505
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
734
if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
740
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
956
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
968
reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
970
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
972
tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
995
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
drivers/gpu/drm/tilcdc/tilcdc_drv.c
418
REG(1, true, LCDC_RASTER_CTRL_REG),