arch/sh/kernel/cpu/sh2a/setup-sh7203.c

143

{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },

arch/sh/kernel/cpu/sh2a/setup-sh7203.c

61

INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),

arch/sh/kernel/cpu/sh3/setup-sh770x.c

62

INTC_VECT(LCDC, 0x9a0),

arch/sh/kernel/cpu/sh3/setup-sh770x.c

83

{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },

arch/sh/kernel/cpu/sh3/setup-sh7720.c

247

INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),

arch/sh/kernel/cpu/sh3/setup-sh7720.c

271

{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },

arch/sh/kernel/cpu/sh4/setup-sh7760.c

111

{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,

arch/sh/kernel/cpu/sh4/setup-sh7760.c

56

INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),

arch/sh/kernel/cpu/sh4/setup-sh7760.c

90

SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

364

INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

388

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

410

{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

302

INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

325

{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

347

{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

577

INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

602

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

624

{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

1030

JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

1060

{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

994

INTC_VECT(LCDC, 0xF40),

arch/sh/kernel/cpu/sh4a/setup-sh7734.c

415

INTC_VECT(LCDC, 0xC40),

arch/sh/kernel/cpu/sh4a/setup-sh7734.c

451

INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */

arch/sh/kernel/cpu/sh4a/setup-sh7734.c

509

{ SCIF0, SCIF3, HSCIF, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

259

INTC_VECT(LCDC, 0x620),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

311

LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

327

{ 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },