drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

629

tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

421

REG_SET_2(LB_MEMORY_CTRL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

250

XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

251

XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

606

uint32_t LB_MEMORY_CTRL;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

93

SRI(LB_MEMORY_CTRL, LB, id), \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1114

uint32_t LB_MEMORY_CTRL; \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

60

SRI(LB_MEMORY_CTRL, DSCL, id), \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

210

REG_SET_2(LB_MEMORY_CTRL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

103

SRI(LB_MEMORY_CTRL, DSCL, id), \

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

202

REG_SET_2(LB_MEMORY_CTRL, 0,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

488

SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

288

SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \

drivers/gpu/drm/radeon/cik.c

8852

WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,