L2
int L1I, L1D, L2, L3;
L2 = external_cache_probe(128*1024, 5);
L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1);
L2 = CSHAPE (96*1024, width, 3);
L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1);
L2 = external_cache_probe(512*1024, 6);
L2 = external_cache_probe(1024*1024, 6);
L2 = CSHAPE(7*1024*1024/4, 6, 7);
L1I = L1D = L2 = L3 = 0;
alpha_l2_cacheshape = L2;
ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);
ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);
ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0);
{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
[BPF_REG_8] = L2,
return L(L2) | LN(L2);
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x05: L2 Hit */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x04: L2 Hit Clean */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT), /* 0x07: L2 Hit Snoop HIT */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM), /* 0x08: L2 Hit Snoop Hit Modified */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x09: Prefetch Promotion */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x0a: Cross Core Prefetch Promotion */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 Hit Clean */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT), /* 0x04: L2 Hit Snoop HIT */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM), /* 0x05: L2 Hit Snoop Hit Modified */
u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
*val |= P(TLB, MISS) | P(TLB, L2);
*val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
val |= P(TLB, MISS) | P(TLB, L2);
val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
val |= P(TLB, MISS) | P(TLB, L2);
val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
val |= P(TLB, MISS) | P(TLB, L2);
val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
{0, L2, 400*1000},
[L2] = {
panthor_gpu_power_off(ptdev, L2, ptdev->gpu_info.l2_present, 20000);
return panthor_gpu_power_on(ptdev, L2, 1, 20000);
LIBIE_RX_PT(L2, NOT_FRAG, NONE, NONE, NOT_FRAG, iprot, pl)
#define LIBIE_RX_PT_L2 __LIBIE_RX_PT_L2(NONE, L2)
#define LIBIE_RX_PT_TS __LIBIE_RX_PT_L2(TIMESYNC, L2)
[0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
[0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2),
[0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
[0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
[0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
[0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
[0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
[0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3);
PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3));
FUNC_GROUP_DECL(ADC3, L2);
ASPEED_PINCTRL_PIN(L2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
ASPEED_PINCTRL_PIN(L2),
SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
PIN_DECL_1(L2, GPIOJ1, SGPMLD);
FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
prdbg(L2);
#define fn_for_each2_XXX(L1, L2, P, FN, ...) \
label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
#define fn_for_each_in_merge(L1, L2, P, FN) \
fn_for_each2_XXX((L1), (L2), P, FN, _in_merge)
#define fn_for_each_not_in_set(L1, L2, P, FN) \
fn_for_each2_XXX((L1), (L2), P, FN, _not_in_set)
#define xcheck_ns_labels(L1, L2, FN, args...) \
fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
#define xcheck_labels_profiles(L1, L2, FN, args...) \
xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
#define xcheck_labels(L1, L2, P, FN1, FN2) \
xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* L2 hit|SNP None */
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* L2 hit|SNP None */
*val |= P(TLB, MISS) | P(TLB, L2);
*val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
if (lvl & P(LVL, L2)) {